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rev: 1.05 7/2001 1/30 ? 1999, giga semiconductor, inc. specifications cited are subject to change without notice. for latest documentation see http://www.gsitechnology.com. trademark notice (if any) trademark of giga semiconductor, inc. (gsi technology). gs84118t/b-166/150/133/100 256k x 18 sync cache tag 166 mhz?100 mhz 8.5 ns?12 ns 3.3 v v dd 3.3 v and 2.5 v i/o tqfp, bga commercial temp industrial temp features ? 3.3 v +10%/?5% core power supply, 2.5 v or 3.3 v i/o supply ? intergrated data comparator for tag ram application ? ft mode pin for flow through or pipeline operation ? lbo pin for linear or interleave (pentium tm and x86) burst mode ? synchronous address, data i/o, and control inputs ? synchronous data enable ( de ) ? asynchronous output enable ( oe ) ? asynchronous match output enable ( moe ) ? byte write ( bwe ) and global write ( gw ) operation ? three chip enable signals for easy depth expansion ? internal self-timed write cycle ? jtag test mode conforms to ieee standard 1149.1 ? jedec-standard 100-lead tqfp package and 119-bga: t :tqfp or b : bga functional description the gs84118 is a 256k x 18 high performance synchronous sram with integrated tag ram comparator. a 2-bit burst counter is included to provide burst interface with pentium tm and other high performance cpus. it is designed to be used as a cache tag sram, as well as data sram. addresses, data ios, match output, chip enables ( ce1 , ce2, ce3 ), address control inputs ( adsp , adsc , adv ), and write control inputs ( bw1 , bw2 , bwe , gw, de ) are synchronous and are controlled by a positive-edge-triggered clock (clk). output enable ( oe ), match output enable, and power down control (zz) are asynchronous. burst can be initiated with either adsp or adsc inputs. subsequent burst addresses are generated internally and are controlled by adv . the burst sequence is either interleave order (pentium tm or x86) or linear order, and is controlled by lbo . output registers and the match output register are provided and controlled by the ft mode pin (pin 14). through use of the ft mode pin, i/o registers can be programmed to perform pipeline or flow through operation. flow through mode reduces latency. byte write operation is performed by using byte write enable ( bwe ) input combined with two individual byte write signals bw 1-2. in addition, global write ( gw ) is available for writing all bytes at one time. compare cycles begin as a read cycle with output disabled so that compare data can be loaded into the data input register. the comparator compares the read data with the registered input data and a match signal is generated. the match output can be either in pipeline or flow through modes controlled by the ft signal. low power (standby mode) is attained through the assertion of the zz signal, or by stopping the clock (clk). memory data is retained during standby mode. jtag boundary scan interface is provided using ieee standard 1149.1 protocol. four pins?test data in (tdi), test data out (tdo), test clock (tck) and test mode select (tms)?are used to perform jtag function. the gs84118 operates on a 3.3 v power supply and all inputs/ outputs are 3.3 v- or 2.5 v-lvttl-compatible. separate output ( v ddq ) pins are used to allow both 3.3 v or 2.5 v io interface. * pentium is a trademark of intel corp. -166 -150 -133 -100 pipeline 3-1-1-1 t cycle t kq i dd 6.0 ns 3.5 ns 310 ma 6.6 ns 3.8 ns 275 ma 7.5 ns 4.0 ns 250 ma 10 ns 4.5 ns 190 ma flow through 2-1-1-1 t kq t cycle i dd 8.5 ns 10 ns 190 ma 10 ns 10 ns 190 ma 11 ns 15 ns 140 ma 12 ns 15 ns 140 ma
rev: 1.05 7/2001 2/30 ? 1999, giga semiconductor, inc. specifications cited are subject to change without notice. for latest documentation see http://www.gsitechnology.com. gs84118t/b-166/150/130/100 pin configuration 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 v ddq v ss dq 9 dq 10 v ss v ddq dq 11 dq 12 v dd nc v ss dq 13 dq 14 v ddq v ss dq 15 dq 16 dq p2 v ss v ddq v ddq v ss dq 8 dq 7 v ss v ddq dq 6 dq 5 v ss nc v dd zz dq 4 dq 3 v ddq v ss dq 2 dq 1 v ss v ddq l b o a 5 a 4 a 3 a 2 a 1 a 0 t m s t d i v s s v d d t d o t c k a 1 5 a 1 4 a 1 3 a 1 2 a 1 1 a 1 7 a 6 a 7 c e 1 c e 2 n c n c b w 2 b w 1 c e 3 c l k g w b w e v d d v s s o e a d s c a d s p a d v a 8 a 9 a 1 6 256k x 18 top view dq p1 a 10 nc nc nc nc nc de m a t c h moe nc nc nc nc nc nc nc nc nc 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 ft
rev: 1.05 7/2001 3/30 ? 1999, giga semiconductor, inc. specifications cited are subject to change without notice. for latest documentation see http://www.gsitechnology.com. gs84118t/b-166/150/130/100 84118 padout 119-bump bga?top view 1 2 3 4 5 6 7 a v ddq a 6 a 7 adsp a 8 a 9 v ddq b nc e 2 a 4 adsc a 15 e 3 nc c nc a 5 a 3 v dd a 14 a 16 nc d dq b1 nc v ss nc v ss dq p1 nc e nc dq b2 v ss e 1 v ss nc dq a8 f v ddq nc v ss g v ss dq a7 v ddq g nc d q b3 b b adv nc nc dq a6 h dq b4 n c v ss gw v ss dq a5 nc j v ddq v dd nc v dd nc v dd v ddq k nc dq b5 v ss ck v ss nc dq a4 l dq b6 nc nc nc b a dq a3 nc m v ddq dq b7 v ss bw v ss match v ddq n dq b8 nc v ss a 1 v ss dq a2 de p nc dq p2 v ss a 0 v ss moe dq a1 r nc a 2 lbo v dd ft a 13 nc t nc a 10 a 11 nc a 12 a 17 zz u v ddq tms tdi nc tdo tck v ddq
rev: 1.05 7/2001 4/30 ? 1999, giga semiconductor, inc. specifications cited are subject to change without notice. for latest documentation see http://www.gsitechnology.com. gs84118t/b-166/150/130/100 tqfp p in d escription pin location symbol description 37, 36, 35, 34, 33, 32, 100, 99, 82, 81, 80, 48, 47, 46, 45, 44, 49, 50 a0?a17 address input signals?inputs are registered and must meet setup and hold times, as specified on page 11 . 89 clk clock input signal 87 bwe byte write enable signal?the byte write enable signal needs to be combined with one of the four byte write signals for a write operation to occur. 93 bw1 byte write signal for data outputs 1 thru 8 94 bw2 byte write signal for data outputs 9 thru 16 88 gw global write enable 92, 97, 98 ce1 ,ce2, ce3 chip enables 86 oe output enable 83 adv burst address advance 84, 85 adsp , adsc address status signals 58, 59, 62 ,63, 68, 69, 72, 73, 8, 9, 12, 13, 18, 19, 22, 23 dq1?dq16 data input and output pins 74, 24 dqp1?dqp2 parity input and output pins 53 match match output 51 moe match output enable 52 de data enable?data input registers are updated only when de is active. 64 zz power down control?application of zz will result in a low standby power consumption. 14 ft flow through or pipeline mode 31 lbo linear order burst mode 38 tms test mode select 39 tdi test data in 42 tdo test data out 43 tck test clock 15, 41, 65, 91 v dd 3.3 v power supply 5,10,17, 21, 26, 40, 55, 60, 67, 71, 76, 90 v ss ground 4, 11, 20, 27, 54, 61, 70, 77 v ddq 2.5 v/3.3 v output power supply 1, 2, 3, 6, 7, 16, 25, 28, 29, 30,56, 57, 66, 75, 78, 79, 95, 96 nc no connect
rev: 1.05 7/2001 5/30 ? 1999, giga semiconductor, inc. specifications cited are subject to change without notice. for latest documentation see http://www.gsitechnology.com. gs84118t/b-166/150/130/100 pbga p in d escription pin location symbol description p4, n4, r2, c3, b3, c2, a2, a3, a5, a6, t6, c5, r6, t5, t2, t3, b5, c6 a0?a17 address input signals?inputs are registered and must meet setup and hold times, as specified on page 11 . k4 clk clock input signal m4 bwe byte write enable signal?the byte write enable signal needs to be combined with one of the four byte write signals for a write operation to occur. l5 bw1 byte write signal for data outputs 1 thru 8 g3 bw2 byte write signal for data outputs 9 thru 16 h4 gw global write enable e4, b2, b6 ce1 ,ce2, ce3 chip enables f4 oe output enable g4 adv burst address advance a4, b4 adsp , adsc address status signals p7, n6, l6, k7, h6, g7, f6, e7, d1, e2, g2, h1, k2, l1, m2, n1 dq1?dq16 data input and output pins d6, p2 dqp1?dqp2 parity input and output pins m6 match match output p6 moe match output enable n7 de data enable?data input registers are updated only when de is active. t7 zz power down control?application of zz will result in a low standby power consumption. r5 ft flow through or pipeline mode r3 lbo linear order burst mode u2 tms test mode select u3 tdi test data in u5 tdo test data out u4 tck test clock c4, j2, j4, j6, r4 v dd 3.3 v power supply d3, d5, e3, e5, f3, f5, h3, h5, k3, k5, m3, m5, n3, n5, p3, p5 v ss ground a1, a7, f1, f7, j1, j7, m1, m7, u1, u7 v ddq 2.5 v/3.3 v output power supply b1, b7, c1, c7, d2, d4, d7, e1, e6, f2, g1, g5, g6, h2, h7, j3, j5, k1, k6, l2, l3, l4, l7, n2, p1, rr1, r7, t1, t4, u6 nc no connect
rev: 1.05 7/2001 6/30 ? 1999, giga semiconductor, inc. specifications cited are subject to change without notice. for latest documentation see http://www.gsitechnology.com. gs84118t/b-166/150/130/100 functional block diagram a1 a0 a0 a1 d0 d1 q1 q0 b i n a r y c o u n t e r load d q r e g i s t e r d q register d q register d q register d q register d q register d q r e g i s t e r d q r e g i s t e r a0-17 lbo adv clk adsc adsp gw bwe bw1 bw2 ce1 ce2 ce3 ft dq1-16 oe zz powerdown control 256k x 18 memory array 18 18 18 18 2 18 a q d dqp1-2 de d q r e g i s t e r match tap controller instruction reg. id reg. bypass reg boundary scan registers 54 tck tms tdi a, dq, control tdo moe
rev: 1.05 7/2001 7/30 ? 1999, giga semiconductor, inc. specifications cited are subject to change without notice. for latest documentation see http://www.gsitechnology.com. gs84118t/b-166/150/130/100 mode pin function lbo function l linear burst h or nc interleaved burst ft function l flow through h or nc pipeline power down control note: there are pull up devices on lbo and ft pins and pull down device on zz pin, so those input pins can be unconnected and the chip will operate in the default states as specified in the above tables. zz function l or nc active h standby, idd = isb linear burst sequence a[1:0] a[1:0] a[1:0] a[1:0] 1st address 00 01 10 11 2nd address 01 10 11 00 3rd address 10 11 00 01 4th address 11 00 01 10 interleaved burst sequence a[1:0] a[1:0] a[1:0] a[1:0] 1st address 00 01 10 11 2nd address 01 00 11 10 3rd address 10 11 00 01 4th address 11 10 01 00 byte write function note: h = logic high, l = logic low, nc = no connect function gw bwe bw1 bw2 read h h x x read h l h h write all bytes l x x x write all bytes h l l l write byte 1 h l l h write byte 2 h l h l
rev: 1.05 7/2001 8/30 ? 1999, giga semiconductor, inc. specifications cited are subject to change without notice. for latest documentation see http://www.gsitechnology.com. gs84118t/b-166/150/130/100 synchronous truth table notes: 1. x means ?don?t care,? h means ?logic high,? l means ?logic low.? 2. write is the logic function of gw , bwe , bw1 , bw2 . see byte write function table for detail. 3. all inputs, except oe , must meet setup and hold on rising edge of clk. 4. suspending busrt generates a wait cycle. 5. adsp low along with sram being selected always initiates a read cycle at the l-h edge of the clock (clk). 6. a write cycle can only be performed by setting write low for the clock l-h edge of the subsequent wait cycle. refer to page 12 for the write timing diagram. operation address used ce1 ce2 ce3 adsp adsc adv write oe clk dq deselect cycle, power down none h x x x l x x x l-h high-z deselect cycle, power down none l l x l x x x x l-h high-z deselect cycle, power down none l x h l x x x x l-h high-z deselect cycle, power down none l l x h l x x x l-h high-z deselect cycle, power down none l x h h l x x x l-h high-z read cycle, begin burst external l h l l x x x l l-h q read cycle, begin burst external l h l l x x x h l-h high-z read cycle, begin burst external l h l h l x h l l-h q read cycle, begin burst external l h l h l x h h l-h high-z write cycle, begin burst external l h l h l x l x l-h d read cycle, continue burst next x x x h h l h l l-h q read cycle, continue burst next x x x h h l h h l-h high-z read cycle, continue burst next h x x x h l h l l-h q read cycle, continue burst next h x x x h l h h l-h high-z write cycle, continue burst next x x x h h l l x l-h d write cycle, continue burst next h x x x h l l x l-h d read cycle, suspend burst current x x x h h h h l l-h q read cycle, suspend burst current x x x h h h h h l-h high-z read cycle, suspend burst current h x x x h h h l l-h q read cycle, suspend burst current h x x x h h h h l-h high-z write cycle, suspend burst current x x x h h h l x l-h d write cycle, suspend burst current h x x x h h l x l-h d
rev: 1.05 7/2001 9/30 ? 1999, giga semiconductor, inc. specifications cited are subject to change without notice. for latest documentation see http://www.gsitechnology.com. gs84118t/b-166/150/130/100 truth table for read/write/compare/fill write operation notes: 1. x means ?don?t care,? h means ?logic high,? l means ?logic low.? 2. write is the logic function of gw , bwe , bw1 , bw2 . see byte write function table for detail. 3. ce is defined as ce1 =l, ce2=h and ce3 =l 4. all signals are synchronous and are sampled by clk except oe and moe . oe and moe are asynchronous and drive the bus immediately. absolute maximum ratings (voltage reference to v ss = 0 v) note: permanent damage to the device may occur if the absolute maximun ratings are exceeded. functional operation should be rest ricted to the recommended operation conditions. exposure to higher than recommended voltages, for an extended period of time, could effect the performance and reliability of this component. ce write de moe oe match dq read l h x x l ? q write l l l x h ? d compare l h l l h data out d fill write l l h x x ? x match deselect h x x l x high high z deselect h x x h x high z high z symbol description commerical unit v dd supply voltage ?0.5 to 4.6 v v ddq output supply voltage ?0.5 to v dd v v clk clk input voltage ?0.5 to 6 v v in input voltage ?0.5 to v dd + 0.5 ( 4.6 v max. ) v v out output voltage ?0.5 to v dd + 0.5 ( 4.6 v max. ) v i out output current per i/o +/?20 ma p d power dissipation 1.5 w t opr operating temperature 0 to 70 o c t stg storage temperature ?55 to 125 o c
rev: 1.05 7/2001 10/30 ? 1999, giga semiconductor, inc. specifications cited are subject to change without notice. for latest documentation see http://www.gsitechnology.com. gs84118t/b-166/150/130/100 package thermal characteristics notes: 1. junction temperature is a function of sram power dissapation, package thermal resistance, mounting board temperature, ambient. temperature air flow, board density, and pcb thermal resistance. 2. scmi g-38-87. 3. average thermal resistance between die and top surface, mil spec-883, method 1012.1. rating layer board symbol tqfp max pbga max unit notes junction to ambient (at 200 lfm) single r q ja 32 28 c/w 1,2 junction to ambient (at 200 lfm) four r q ja 20 18 c/w 1,2 junction to case (top) ? r q jc 7 4 c/w 3 ac test conditions (v dd = 3.135 v?3.6 v, t a = 0?70 c) notes: 1. include scope and jig capacitance. 2. test conditions as specified with output loading as shown in fig. 1 unless otherwise noted. 3. output load 2 for t lz , t hz , t olz and t ohz . 4. device is deselected as defined by the truth table. parameter conditions input high level v ih = 2.3 v input low level v il = 0.2 v input slew rate tr = 1 v/ns input reference level 1.25 v output reference level 1.25 v output load fig. 1& 2 dq vt = 1.25 v 5 0 w 30 pf 1 dq 2.5 v f i g . 1 output load 1 output load 2 f i g . 2 225 w 225 w 5 pf 1
rev: 1.05 7/2001 11/30 ? 1999, giga semiconductor, inc. specifications cited are subject to change without notice. for latest documentation see http://www.gsitechnology.com. gs84118t/b-166/150/130/100 dc characteristics and supply currents (voltage reference to v ss = 0 v) (v dd = 3.135 v?3.6 v, ta = 0?70 c for commercial temperature offering) parameter symbol test conditions min max input leakage current (except zz, ft , lbo pins) i il v in = 0 to v dd ?1 ua 1 ua zz input current iin zz v dd 3 v in 3 v ih 0 v v in v ih ?1 ua ?1 ua 1 ua 300 ua mode input current ( ft & lbo pins) iin m v dd 3 v in 3 v il 0 v v in v il ?30 0ua ?1 ua 1 ua 1 ua output leakage current i ol output disable, v out = 0 to v dd ?1 ua 1 ua output high voltage v oh i oh = ?4 ma, v ddq = 2.375 v 1.7 v output high voltage v oh i oh = ?4 ma, v ddq = 3.135 v 2.4 v output low voltage v ol i ol = +4 ma 0.4 v
rev: 1.05 7/2001 12/30 ? 1999, giga semiconductor, inc. specifications cited are subject to change without notice. for latest documentation see http://www.gsitechnology.com. gs84118t/b-166/150/130/100 operating currents parameter test conditions symbol -166 -150 -133 -100 unit 0 to 70 c ?40 to +85 c 0 to 70 c ?40 to +85 c 0 to 70 c ?40 to +85 c 0 to 70 c ?40 to +85 c o perating current device selected; all other inputs 3 v ih o r v il output open i dd pipeline 310 320 275 285 250 260 190 200 ma i dd flow through 190 200 190 200 140 150 140 150 ma standby current zz 3 v dd ? 0.2 v i sb pipeline 30 40 30 40 30 40 30 40 ma i sb flow through 30 40 30 40 30 40 30 40 ma deselect supply current device deselected; all other inputs 3 v ih o r v il i dd pipeline 110 120 105 115 100 110 80 90 ma i dd flow through 80 90 80 90 65 75 65 75 ma
rev: 1.05 7/2001 13/30 ? 1999, giga semiconductor, inc. specifications cited are subject to change without notice. for latest documentation see http://www.gsitechnology.com. gs84118t/b-166/150/130/100 ac electrical characteristics parameter symbol -166 -150 -133 -100 unit min max min max min max min max pipeline clock cycle time tkc 6.0 ? 6.7 ? 7.5 ? 10 ? ns clock to output valid tkq ? 3.5 ? 3.8 ? 4 ? 4.5 ns clock to output invalid tkqx 1.5 ? 1.5 ? 1.5 ? 1.5 ? ns clock to output in low-z tlz 1 1.5 ? 1.5 ? 1.5 ? 1.5 ? ns clock to match valid tkm ? 3.5 ? 3.8 ? 4 ? 4.5 ns clock to match invalid tkmx 1.5 ? 1.5 ? 1.5 ? 1.5 ? ns clock to match in low-z tmlz 1 1.5 ? 1.5 ? 1.5 ? 1.5 ? ns flow-thru clock cycle time tkc 10.0 ? 10.0 ? 15.0 ? 15.0 ? ns clock to output valid tkq ? 8.5 ? 10.0 ? 11.0 ? 12.0 ns clock to output invalid tkqx 3.0 ? 3.0 ? 3.0 ? 3.0 ? ns clock to output in low-z tlz 1 3.0 ? 3.0 ? 3.0 ? 3.0 ? ns clock to match valid tkm ? 8.5 ? 10.0 ? 11.0 ? 12.0 ns clock to match invalid tkmx 3.0 ? 3.0 ? 3.0 ? 3.0 ? ns clock to match in low-z tmlz 1 3.0 ? 3.0 ? 3.0 ? 3.0 ? ns clock high time tkh 1.3 ? 1.5 ? 1.7 ? 2 ? ns clock low time tkl 1.5 ? 1.7 ? 1.9 ? 2.2 ? ns clock to output in high-z thz 1 1.5 3.5 1.5 3.8 1.5 4 1.5 5 ns oe to output valid toe ? 3.5 ? 3.8 ? 4 ? 5 ns oe to output in low-z tolz 1 0 ? 0 ? 0 ? 0 ? ns oe to output in high-z tohz 1 ? 3.5 ? 3.8 ? 4 ? 5 ns moe to match valid tmoe ? 3.5 ? 3.8 ? 4 ? 5 ns moe to match in low-z tmolz 1 0 ? 0 ? 0 ? 0 ? ns moe to match in high-z tmohz 1 ? 3.5 ? 3.8 ? 4 ? 5 ns
rev: 1.05 7/2001 14/30 ? 1999, giga semiconductor, inc. specifications cited are subject to change without notice. for latest documentation see http://www.gsitechnology.com. gs84118t/b-166/150/130/100 notes: 1. these parameters are sampled and are not 100% tested 2. zz is an asynchronous signal. however, in order to be recognized on any given clock cycle, zz must meet the specified setup and hold times as specified above. setup time ts 1.5 ? 1.5 ? 2.0 ? 2.0 ? ns hold time th 0.5 ? 0.5 ? 0.5 ? 0.5 ? ns zz setup time tzzs 2 5 ? 5 ? 5 ? 5 ? ns zz hold time tzzh 2 1 ? 1 ? 1 ? 1 ? ns zz recovery tzzr 20 ? 20 ? 20 ? 20 ? ns ac electrical characteristics parameter symbol -166 -150 -133 -100 unit min max min max min max min max
rev: 1.05 7/2001 15/30 ? 1999, giga semiconductor, inc. specifications cited are subject to change without notice. for latest documentation see http://www.gsitechnology.com. gs84118t/b-166/150/130/100 clk adsp adsc adv gw ce1 bwe ce3 oe wr2 wr3 wr1 wr1 wr2 wr3 t kc single writ e burst write d2a d2b d2c d2d d3a d1a t kl t kh t s t h t s t h t s t h t s t h t s t h t s t h t s t h t s t h t s t h t s t h t s t h write specified byte for 2a and all bytes for 2b, 2c& 2d ce2 and ce3 only sampled with adsp or adsc ce1 masks adsp adv must be inactive for adsp write adsc initiated write adsp is blocked by ce1 inactive write cycle timing a0?a17 bw1 ? bw2 ce2 dq1?16 write deselected hi-z wr1 wr2 wr3 deselected with ce2 dqp1?2 de t s t h
rev: 1.05 7/2001 16/30 ? 1999, giga semiconductor, inc. specifications cited are subject to change without notice. for latest documentation see http://www.gsitechnology.com. gs84118t/b-166/150/130/100 q1a q3a q2d q2c q2b q2a t kq t lz t oe t ohz t olz t kqx t hz t kqx clk adsp adsc bwe oe gw adv ce2 single read rd2 rd3 t kl t s t h t h t h t s t h t h t s t h t s t h adsc initiated read suspend burst ce1 masks adsp ce2 and ce3 only sampled with adsp or adsc deselected with ce2 single read adsp is blocked by ce1 inactive a0?a17 bw1 ? ce3 ce1 t kh t kc t s t h t s t s t h bw2 dq1?16 t s t s rd1 hi-z suspend burst dqp1?2 flow through?read cycle timing
rev: 1.05 7/2001 17/30 ? 1999, giga semiconductor, inc. specifications cited are subject to change without notice. for latest documentation see http://www.gsitechnology.com. gs84118t/b-166/150/130/100 clk adsp adsc adv gw bwe ce1 ce3 oe ce2 rd1 wr1 rd2 wr1 q1a d1a q2a q2b q2c q2d single read burst read t oe t ohz t s t s t h t s t s t h t s t h t h t s t h t s t h t s t h t s t h t kh adsc initiated read ce1 masks adsp ce2 and ce3 only sampled with adsp and adsc deselected with ce3 dq1?16 bw1 ? bw2 a0?a17 t kl t kc t s t h t h s ingle write adsp is blocked by ce1 inactive t kq t s t h hi-z q2a burst wrap around to its initial state dqp1?2 flow through?read/write cycle timing t s t h de
rev: 1.05 7/2001 18/30 ? 1999, giga semiconductor, inc. specifications cited are subject to change without notice. for latest documentation see http://www.gsitechnology.com. gs84118t/b-166/150/130/100 q1a q3a q2d q2c q2b q2a t kq t lz t oe t ohz t olz t kqx t hz t kqx clk adsp adsc bwe oe gw adv ce2 burst read rd2 rd3 t kl t s t h t h t h t s t h t h t s t h t s t h adsc initiated read suspend burst ce1 masks adsp ce2 and ce3 only sampled with adsp or adsc deselected with ce2 single read adsp is blocked by ce1 inactive a0?a17 bw1 ? ce3 ce1 t kh t kc t s t h t s t s t h bw4 dq1?16 t s t s rd1 hi-z dqp1?2 pipeline?read cycle timing
rev: 1.05 7/2001 19/30 ? 1999, giga semiconductor, inc. specifications cited are subject to change without notice. for latest documentation see http://www.gsitechnology.com. gs84118t/b-166/150/130/100 t s t h de clk adsp adsc adv gw bwe ce1 ce3 oe ce2 rd1 wr1 rd2 wr1 q1a d1a q2a q2b q2c q2d single read burst read t oe t ohz t s t s t h t s t s t h t s t h t h t s t h t s t h t s t h t s t h t kh adsc initiated read ce1 masks adsp ce2 and ce3 only sampled with adsp and adsc deselected with ce3 dq1?16 bw1 ? bw4 a0?a17 t kl t kc t s t h t h single write adsp is blocked by ce1 inactive t kq t s t h hi-z dqp1?2 pipeline?read/write cycle timing
rev: 1.05 7/2001 20/30 ? 1999, giga semiconductor, inc. specifications cited are subject to change without notice. for latest documentation see http://www.gsitechnology.com. gs84118t/b-166/150/130/100 hit miss fill write clk ce (1) w (2) oe a0-a17 dq1-16 dqp1-2 de moe match t s t h a b b a b t mlz t moe t km t kmx match high when chip deselected flow through?compare/fill write cycle timing t km t km 2. w = l is the asertive function of gw , bwe , bw1 , bw2 . see byte write function table for detail. 1. ce = l is defined as ce1 =l, ce2=h and ce3 =l notes:
rev: 1.05 7/2001 21/30 ? 1999, giga semiconductor, inc. specifications cited are subject to change without notice. for latest documentation see http://www.gsitechnology.com. gs84118t/b-166/150/130/100 hit miss fill write clk ce (1) w (2) oe a0-a17 dq1-16 dqp1-2 de moe match t s t h a b b a b t mlz t moe t km t kmx match high when chip deselected pipeline?compare/fill write cycle timing 2. w = l is the asertive function of gw , bwe , bw1 , bw2 . see byte write function table for detail. 1. ce = l is defined as ce1=l, ce2=h and ce3=l notes: t km t km
rev: 1.05 7/2001 22/30 ? 1999, giga semiconductor, inc. specifications cited are subject to change without notice. for latest documentation see http://www.gsitechnology.com. gs84118t/b-166/150/130/100 clk adsp adsc t h t kh t kl t kc t s zz t zzr t zzh t zzs ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ snooze zz timing
rev: 1.05 7/2001 23/30 ? 1999, giga semiconductor, inc. specifications cited are subject to change without notice. for latest documentation see http://www.gsitechnology.com. gs84118t/b-166/150/130/100 test mode description functional description the gs84118 provides jtag boundary scan interface using ieee standard 1149.1 protocol. the test mode is intended to provide a mechanism for testing the interconnect between master (processor, controller, etc.), sram, other components and the printed circuit board. test access port (tap) four pins (as defined in pin description tables) are used to performed jtag functions. tdi input is used to scan test data seria lly into one of three registers (instruction register, boundary scan register and bypass register). tdo is the output pin to seriall y output scan test data. the tdi sends the data into the lsb of the selected register and the msb of that register feeds the data to tdo. tms input pin controls the state transition of 16 state tap controllers, as specified in ieee standard 1149.1. inputs on td i and tms are registered on the rising edge of tck clock, and the output data on tdo is presented on the falling edge of tck. the tdo driver is in active state only when tap controller is in shift-ir state or in shift -dr state. tap controller sixteen state controllers are implemented as specified in ieee standard 1149.1. the controller enters the reset state either through ? power up or ? apply logic 1 on tms input pin on 5 consecutive rising edges. select dr capture dr shift dr exit1 dr pause dr exit2 dr update dr select ir capture ir shift ir exit1 ir pause ir exit2 ir update ir test logic reset run test idle 0 0 1 0 1 1 0 0 1 1 1 0 0 1 1 0 0 0 0 1 1 0 0 1 1 0 0 0 1 1 1 1 tap controller state diagram
rev: 1.05 7/2001 24/30 ? 1999, giga semiconductor, inc. specifications cited are subject to change without notice. for latest documentation see http://www.gsitechnology.com. gs84118t/b-166/150/130/100 instruction register (3 bits) the jtag instruction register is consisted of shift register stage and parallel output latch. the register is 3 bits wide and is encoded as follow: bypass register (1 bit) the bypass register is one bit wide and is connected electrically between tdi and tdo and provides the minimum length serially path between tdi and tdo. id register (32 bits) the id register are 32 bits wide and are listed as follow: octal msb ? lsb instruction 0 0 0 0 bypass 1 0 0 1 idcode?read device id 2 0 1 0 sample-z?sample inputs and tri-state dqs, match 3 0 1 1 bypass 4 1 0 0 sample?sample inputs 5 1 0 1 private?manufacturer use only 6 1 1 0 bypass 7 1 1 1 bypass header id[0] 1 gsi id (89 decimal in bank 2) id[7:1] 101 1001 id[11:8] 0001 part number id[27:12] 0000 0000 0000 0000 revision number id[31:28] xxxx
rev: 1.05 7/2001 25/30 ? 1999, giga semiconductor, inc. specifications cited are subject to change without notice. for latest documentation see http://www.gsitechnology.com. gs84118t/b-166/150/130/100 boundary scan register (54 bits) the boundary scan register are 54 bits wide and are listed as follow: scan order (order by exit sequence) dqx, match 19 address 18 gw , bwe , bw 1-2, de 5 ce1 , ce2, ce3 3 oe , moe 2 adsp , adsc , adv 3 zz, ft , lbo 3 clk 1 total 54 order signal tqfp bga order signal tqfp bga 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 a15 a14 a13 a12 a11 a16 a17 moe de match dq1 dq2 dq3 dq4 zz dq5 dq6 dq7 dq8 dqp1 a10 a9 a8 adv adsp adsc oe 44 45 46 47 48 49 50 51 52 53 58 59 62 63 64 68 69 72 73 74 80 81 82 83 84 85 86 3t 2t 5t 6r 5c 5b 6c 6p 7n 6m 7p 6n 6l 7k 7t 6h 7g 6f 7e 6d 6t 6a 5a 4g 4a 4b 4f 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 bwe gw clk ce3 bw1 bw2 ce2 ce1 a7 a6 dq9 dq10 dq11 dq12 ft dq13 dq14 dq15 dq16 dqp2 lbo a5 a4 a3 a2 a1 a0 87 88 89 92 93 94 97 98 99 100 8 9 12 13 14 18 19 22 23 24 31 32 33 34 35 36 37 4m 4h 4k 6b 5l 3g 2b 4e 3a 2a 1d 2e 2g 1h 5r 2k 1l 2m 1n 2p 3r 2c 3b 3c 2r 4n 4p
rev: 1.05 7/2001 26/30 ? 1999, giga semiconductor, inc. specifications cited are subject to change without notice. for latest documentation see http://www.gsitechnology.com. gs84118t/b-166/150/130/100 test mode ac electrical characteristics test mode timing diagram parameter symbol min max unit tck cycle time ttkc 20 ? ns tck low to tdo valid ttkq ? 10 ns tck high pulse width ttkh 10 ? ns tck low pulse width ttkl 10 ? ns tdi & tms set up time tts 5 ? ns tdi & tms hold time tth 5 ? ns t tkc t tkq t ts t th t tkh t tkl tck tms tdi tdo
rev: 1.05 7/2001 27/30 ? 1999, giga semiconductor, inc. specifications cited are subject to change without notice. for latest documentation see http://www.gsitechnology.com. gs84118t/b-166/150/130/100 package dimensions?100-pin tqfp d 1 d e1 e p i n 1 b e c l l1 a2 a1 y q symbol description min. nom. max a1 standoff 0.05 0.10 0.15 a2 body thickness 1.35 1.40 1.45 b lead width 0.20 0.30 0.40 c lead thickness 0.09 0.20 d terminal dimension 21.9 22.0 22.1 d1 package body 19.9 20.0 20.1 e terminal dimension 15.9 16.0 16.1 e1 package body 13.9 14.0 14.1 e lead pitch 0.65 l foot length 0.45 0.60 0.75 l1 lead length 1.00 y coplanarity 0.10 q lead angle 0 7 notes: 1. all dimesnions are in millimeters (mm). 2. package wideth and length do not include mold protrusion.
rev: 1.05 7/2001 28/30 ? 1999, giga semiconductor, inc. specifications cited are subject to change without notice. for latest documentation see http://www.gsitechnology.com. gs84118t/b-166/150/130/100 package dimesions - 119 pin pbga bpr 1999.05.18 n p a b pin 1 corner k e f c t a b c d e f g h j k l m n p r t u g s d 1 2 3 4 5 6 7 package dimesions - 119 pin pbga unit: mm symbo l description min . nom . ma x a width 13.8 14.0 14.2 b length 21.8 22.0 22.2 c package height (including ball) - 2.40 d ball size 0.60 0.75 0.90 e ball height 0.50 0.60 0.70 f package height (excluding balls) 1.46 1.70 g width between balls 1.27 k package height above board 0.80 0.90 1.00 n cut-out package width 12.00 p foot length 19.50 r width of package between balls 7.62 s length of package between balls 20.32 t variance of ball height 0.15 bottom view r top view side view
rev: 1.05 7/2001 29/30 ? 1999, giga semiconductor, inc. specifications cited are subject to change without notice. for latest documentation see http://www.gsitechnology.com. gs84118t/b-166/150/130/100 ordering information org part number 1 type package speed 2 (mhz/ns) t a 3 status 256k x 18 gs84118t-166 pipeline/flow through tqfp 166/8.5 c 256k x 18 gs84118t-150 pipeline/flow through tqfp 150/10 c 256k x 18 gs84118t-133 pipeline/flow through tqfp 133/11 c 256k x 18 gs84118t-100 pipeline/flow through tqfp 100/12 c 256k x 18 gs84118t-166i pipeline/flow through tqfp 166/8.5 i 256k x 18 gs84118t-150i pipeline/flow through tqfp 150/10 i 256k x 18 gs84118t-133i pipeline/flow through tqfp 133/11 c 256k x 18 gs84118t-100i pipeline/flow through tqfp 100/12 i 256k x 18 gs84118b-166 pipeline/flow through bga 166/8.5 c 256k x 18 gs84118b-150 pipeline/flow through bga 150/10 c 256k x 18 gs84118b-133 pipeline/flow through bga 133/11 c 256k x 18 gs84118b-100 pipeline/flow through bga 100/12 c 256k x 18 gs84118b-166i pipeline/flow through bga 166/8.5 i 256k x 18 GS84118B-150I pipeline/flow through bga 150/10 i 256k x 18 gs84118i-133i pipeline/flow through bga 133/11 c 256k x 18 gs84118b-100i pipeline/flow through bga 100/12 i notes: 1. customers requiring delivery in tape and reel should add the character ?t? to the end of the part number. example: gs84032t-7.5t. 2. the speed column indicates the cycle frequency (mhz) of the device in pipelined mode and the latency (ns) in flow through mode. each device is pipeline / flow through mode selectable by the user. 3. t a = c = commercial temperature range. t a = i = industrial temperature range. 4. gsi offers other versions this type of device in many different configurations and with a variety of different features, only some of which are covered in this data sheet. see the gsi technology web site for a complete listing of current offerings.
rev: 1.05 7/2001 30/30 ? 1999, giga semiconductor, inc. specifications cited are subject to change without notice. for latest documentation see http://www.gsitechnology.com. gs84118t/b-166/150/130/100 4mb synchronous tag ram datasheet revision history rev. code: old;new types of changes format or content page /revisions;reason gs84118-2000207; 84118_r1_01 content ? updated bga pin description to meet jedec standard 84118_r1_02; 84118_r1_03 content/format ? updated format to comply with technical publications standards ? corrected typo in tqfp package description table on page 27 84118_r1_03; 84118_r1_04 content ? updated pinout on page 3 ? updated pin description tables for tqfp and pbga ? added overbar to all references of bwe , bw1 , bw2 , gw , ce1 , ce3 , oe , adv , adsp , adsc , moe , de , ft , and lbo ? removed v dd note from ac electrical characteristics table ? imported up-to-date package drawing for 119 pbga 84118_r1_04; 84118_r1_05 content ? reordered pin location listings in pin description tables on pages 4 and 5 ? removed global write reference from bwe description in pin description tables ? removed bwe reference from gw description in pin description tables ? placed overbars on write references in synchronous truth table

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